The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Jun. 24, 2013
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Louis Nervegna, Andover, MA (US);

Bruce Del Signore, Hollis, NH (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 17/10 (2006.01); H03M 3/00 (2006.01); G01N 27/26 (2006.01); G01R 27/26 (2006.01); G01D 5/24 (2006.01);
U.S. Cl.
CPC ...
H03M 3/362 (2013.01); G01N 27/26 (2013.01); G01R 17/105 (2013.01); G01R 27/2605 (2013.01); H03M 3/464 (2013.01); H03M 3/476 (2013.01); H03M 3/496 (2013.01); G01D 5/24 (2013.01); Y10T 307/729 (2015.04);
Abstract

A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.


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