The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Apr. 23, 2018
Applicant:

Georgia Tech Research Corporation, Atlanta, GA (US);

Inventors:

Chenyun Pan, Atlanta, GA (US);

Sourav Dutta, Atlanta, GA (US);

Azad Naeemi, Atlanta, GA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01F 10/32 (2006.01); H03K 19/20 (2006.01); H01F 10/14 (2006.01); H01F 10/16 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
H03K 19/20 (2013.01); H01F 10/14 (2013.01); H01F 10/16 (2013.01); H01F 10/3218 (2013.01); H01L 27/22 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01);
Abstract

Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.


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