The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Mar. 30, 2017
Applicants:
Junghoon Bak, Suwon-si, KR;
Myoungsu Son, Yongin-si, KR;
Boyoung Seo, Suwon-si, KR;
Inventors:
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/12 (2006.01); G11C 14/00 (2006.01); H01L 29/82 (2006.01); G11C 11/56 (2006.01); G11C 19/02 (2006.01); H01L 27/22 (2006.01); G11C 11/15 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); G11C 11/15 (2013.01); G11C 11/5607 (2013.01); G11C 14/0036 (2013.01); G11C 19/02 (2013.01); H01L 27/222 (2013.01); H01L 27/224 (2013.01); H01L 29/82 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); G11C 2211/5615 (2013.01);
Abstract
Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.