The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Dec. 05, 2017
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Sunghan Cho, Seoul, KR;
Shinhwan Kang, Seoul, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11565 (2017.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11565 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53271 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/0847 (2013.01);
Abstract
A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.