The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Jun. 06, 2017
Applicant:

Samsung Electronics Co. Ltd., Suwon-si, KR;

Inventors:

Junggil Yang, Suwon-si, KR;

Sangsu Kim, Yongin-si, KR;

TaeYong Kwon, Suwon-Si, KR;

Sung Gi Hur, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/30604 (2013.01); H01L 21/30612 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0922 (2013.01); H01L 29/42392 (2013.01); H01L 29/1054 (2013.01);
Abstract

A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.


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