The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Oct. 13, 2015
Applicant:
Violin Systems Llc, San Jose, CA (US);
Inventor:
Jon C. R. Bennett, Sudbury, MA (US);
Assignee:
VIOLIN SYSTEMS LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 11/4076 (2006.01); G06F 1/32 (2006.01); G11C 5/04 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/3203 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 3/064 (2013.01); G06F 3/0608 (2013.01); G06F 3/0652 (2013.01); G06F 3/0688 (2013.01); G06F 3/0689 (2013.01); G11C 5/04 (2013.01); G11C 11/406 (2013.01); G11C 11/4074 (2013.01); G11C 11/40611 (2013.01); G06F 2212/7202 (2013.01); G11C 2211/4067 (2013.01); Y02D 10/13 (2018.01); Y02D 10/14 (2018.01); Y02D 50/20 (2018.01);
Abstract
A memory system is described, where a plurality of memory modules is connected to a memory controller. Erase operations of the memory modules are coordinated by the memory controller such that, when data is stored in a group of memory modules configured to be a RAID (Redundant Array of Independent 'Disks') group, erase or refresh operations performed on the memory modules of the RAID group are synchronized, scheduled, or controlled to reduce the latency in reading the data stored on the RAID modules.