The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Jan. 02, 2018
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Guangyan Luo, Shanghai, CN;

Hao Ni, Shanghai, CN;

Chuntian Yu, Shanghai, CN;

Xiaoyan Liu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/12 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 7/14 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 8/10 (2013.01);
Abstract

A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.


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