The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Oct. 21, 2014
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Paul Bowden, Berlin, MA (US);

Arthur J. Beaverson, Boxborough, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/30 (2006.01); G06F 12/1045 (2016.01); G06F 12/02 (2006.01); G06F 12/0864 (2016.01); G06F 12/0875 (2016.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1054 (2013.01); G06F 12/0246 (2013.01); G06F 12/0864 (2013.01); G06F 12/0875 (2013.01); G06F 12/1408 (2013.01); G06F 17/30097 (2013.01); G06F 17/30949 (2013.01); G06F 17/30952 (2013.01); G06F 2212/2542 (2013.01); G06F 2212/402 (2013.01); G06F 2212/452 (2013.01); G06F 2212/502 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/7211 (2013.01);
Abstract

Method and apparatus for constructing an index that scales to a large number of records and provides a high transaction rate. New data structures and methods are provided to ensure that an indexing algorithm performs in a way that is natural (efficient) to the algorithm, while a non-uniform access memory device sees IO (input/output) traffic that is efficient for the memory device. One data structure, a translation table, is created that maps logical buckets as viewed by the indexing algorithm to physical buckets on the memory device. This mapping is such that write performance to non-uniform access SSD and flash devices is enhanced. Another data structure, an associative cache is used to collect buckets and write them out sequentially to the memory device as large sequential writes. Methods are used to populate the cache with buckets (of records) that are required by the indexing algorithm. Additional buckets may be read from the memory device to cache during a demand read, or by a scavenging process, to facilitate the generation of free erase blocks.


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