The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Apr. 21, 2016
International Business Machines Corporation, Armonk, NY (US);
Rodrigo Alvarez-Icaza Rivera, San Jose, CA (US);
John V. Arthur, Mountain View, CA (US);
John E. Barth, Jr., Williston, VT (US);
Andrew S. Cassidy, San Jose, CA (US);
Subramanian Iyer, Mount Kisco, NY (US);
Paul A. Merolla, Palo Alto, CA (US);
Dharmendra S. Modha, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.