The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Dec. 28, 2015
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

G. Glenn Henry, Austin, TX (US);

Darius D. Gaskins, Austin, TX (US);

Assignee:

VIA TECHNOLOGIES, INC., New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 1/24 (2006.01); G06F 13/36 (2006.01); G06F 15/163 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 9/445 (2018.01); G06F 15/82 (2006.01); G06F 11/36 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/24 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/30076 (2013.01); G06F 9/30083 (2013.01); G06F 9/44505 (2013.01); G06F 9/5094 (2013.01); G06F 13/36 (2013.01); G06F 15/163 (2013.01); G06F 15/82 (2013.01); G06F 11/1423 (2013.01); G06F 11/3664 (2013.01); Y02D 10/14 (2018.01); Y02D 10/22 (2018.01);
Abstract

A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.


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