Power mapping and modeling system for integrated circuits

Abstract

This invention relates to a power mapping and modeling system for integrated circuits. An automated process includes determining a floor plan of the integrated circuit, dividing the integrated circuit into blocks based on the floor plan, pumping oil through an inlet valve, over the integrated circuit, and out an outlet valve to create a simulated oil-based cooling system, injecting a plurality of power pulses across the integrated circuit, applying infrared image techniques to the integrated circuit to create measured thermal images for the simulated oil-based cooling system, setting up a finite-element model (FEM) to estimate entries in a first thermal-to-power modeling matrix for the simulated oil-based cooling system, determining and storing performance monitoring counter (PMC) measurements related to power consumptions of the blocks of the integrated circuit, reconstructing a power dissipation for the simulated oil-based cooling system by using a thermal map for the simulated oil-based cooling system system, using the power dissipation of the simulated oil-based cooling system, the FEM, and the PMC measurements to create a thermal map for a copper based cooling system, and creating a final thermal-to-power model for the integrated circuit from the thermal map for the model copper based cooling system.