The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Jul. 30, 2015
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
James Deas, Edinburgh, GB;
Jean Lasseuguette, Edinburgh, GB;
John Pennock, Edinburgh, GB;
Mark Hesketh, Edinburgh, GB;
Cirrus Logic, Inc., Austin, TX (US);
Abstract
This application relates to an integrated circuit die () comprising a MEMS transducer structure () integrated with associated electronic circuitry (). The electronic circuitry comprises a plurality of transistors and associated interconnections and is formed in a first area () of the die from a first plurality () of layers, e.g. formed by CMOS metal () and dielectric () layers and possibly doped areas () of substrate (). The MEMS transducer structure is formed in a second area () of the die and is formed, at least partly, from a second plurality () of layers which are separate to the first plurality of layers. At least one filter circuit () is formed from said second plurality of layers overlying the plurality of transistors of the electronic circuitry (). The second plurality of layers comprise at least a first metal layer () which is patterned to form a first electrode of the MEMS transducer and at least a resistor, capacitor electrode or inductor element () of the filter circuit.