The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Nov. 20, 2017
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventor:

Kuan-Yu Shih, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45224 (2013.01); H03F 1/0211 (2013.01); H03F 3/4565 (2013.01); H03F 3/45475 (2013.01); H03F 3/45636 (2013.01); H03F 3/45654 (2013.01); H03F 2200/144 (2013.01); H03F 2200/267 (2013.01); H03F 2200/48 (2013.01); H03F 2203/45031 (2013.01); H03F 2203/45032 (2013.01); H03F 2203/45151 (2013.01); H03F 2203/45156 (2013.01); H03F 2203/45276 (2013.01); H03F 2203/45404 (2013.01); H03F 2203/45418 (2013.01); H03F 2203/45424 (2013.01); H03F 2203/45692 (2013.01);
Abstract

An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.


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