The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Feb. 14, 2017
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Chulho Kim, Daejeon, KR;

Dong Seung Kwon, Daejeon, KR;

Bonghyuk Park, Daejeon, KR;

Young-Kyun Cho, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/868 (2006.01); H01L 23/528 (2006.01); H01L 23/66 (2006.01); H01L 27/08 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/868 (2013.01); H01L 23/5286 (2013.01); H01L 23/66 (2013.01); H01L 27/0814 (2013.01); H01L 29/0649 (2013.01); H01L 2223/6627 (2013.01);
Abstract

A vertical positive-intrinsic-negative (pin) diode includes a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed therein, a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region, and a second electrode formed on the other surface of the semiconductor substrate to be in electrical contact with the N-type region, wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other.


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