The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Oct. 15, 2014
Applicant:

Cmosis Bvba, Antwerp, BE;

Inventors:

Guy Meynants, Retie, BE;

Jan Bogaerts, Waver, BE;

Assignee:

CMOSIS BVBA, Antwerp, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/146 (2006.01); H04N 5/232 (2006.01); H04N 5/355 (2011.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14643 (2013.01); H01L 27/14609 (2013.01); H04N 5/23245 (2013.01); H04N 5/3559 (2013.01); H04N 5/37452 (2013.01);
Abstract

An image sensor comprises an array of pixels comprising: a pinned photodiode; a first sense node A; a second sense node B; a transfer gate TX connected between the pinned photodiode and the first sense node A; a first reset transistor Mconnected between a voltage reference line Vrst and the second sense node B; a second reset transistor Mconnected between the first sense node A and the second sense node B; and a buffer amplifier Mhaving an input connected to the first sense node A. The control logic is arranged to operate the pixels in a low conversion gain mode and in a high conversion gain mode. In each of the conversion gain modes the control logic is arranged to operate one of a first reset control line RSand a second reset control line RSto continuously switch on one of the first reset transistor Mand the second reset transistor Mduring a readout period of an operational cycle of the pixels.


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