The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jul. 25, 2016
Applicant:

Hitachi Automotive Systems, Ltd., Ibaraki, JP;

Inventors:

Katsumi Ikegaya, Hitachinaka, JP;

Takayuki Oshima, Hitachinaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 21/3205 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01F 7/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 21/28 (2013.01); H01L 21/3205 (2013.01); H01L 21/768 (2013.01); H01L 23/522 (2013.01); H01L 23/5226 (2013.01); H01L 27/088 (2013.01); H01L 29/78 (2013.01); H01F 7/064 (2013.01);
Abstract

On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.


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