The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Dec. 10, 2013
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Ming Zhang, Beijing, CN;

Guoqi Mao, Beijing, CN;

Zhaohui Hao, Beijing, CN;

Woong Sun Yoon, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 22/30 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); G02F 2001/136254 (2013.01);
Abstract

An array substrate and a display device are provided. The array substrate includes a display region and a peripheral circuit region, wherein a first gate line, a first data line and a pixel region are arranged in the display region; the pixel region includes a first pixel electrode and a thin film transistor, and the thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode; the peripheral circuit region is provided with at least one test unit including: a second gate line; a second data line; a second testing pixel electrode; and a second testing thin film transistor. The second testing thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode, wherein the second gate electrode, the second source electrode and the second drain electrode are provided with test ports exposed outside.


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