The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jun. 06, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Sung Hwa Ok, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G11C 11/4099 (2006.01); G11C 11/4074 (2006.01); G11C 11/4093 (2006.01); G11C 7/10 (2006.01); G11C 16/30 (2006.01); G11C 14/00 (2006.01); G11C 5/14 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4099 (2013.01); G11C 7/1084 (2013.01); G11C 11/4074 (2013.01); G11C 11/4082 (2013.01); G11C 11/4093 (2013.01); G11C 16/30 (2013.01); G11C 5/147 (2013.01); G11C 14/00 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01);
Abstract

Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device including a plurality of memory cells using an optimal input buffer reference voltage may include at least one input buffer receiving data to be stored in the plurality of memory cells, and an input buffer reference voltage control unit setting one of a plurality of internal voltages generated beforehand and having different voltage levels as a reference voltage of the at least one input buffer in response to a control signal received from a controller controlling the semiconductor memory device.


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