The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Aug. 17, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ekaterina M. Ambroladze, Los Angeles, CA (US);

Norbert Hagspiel, Wendlingen, DE;

Sascha Junghans, Ammerbuch, DE;

Matthias Klein, Boeblingen, DE;

Jeorg Walter, Tuebingen, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 13/38 (2006.01); G06F 12/0862 (2016.01); G06F 12/084 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 12/084 (2013.01); G06F 12/0862 (2013.01); G06F 2212/6028 (2013.01);
Abstract

A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.


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