The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jun. 30, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Michelle E. Zeng, San Jose, CA (US);

Subodh Kumar, San Jose, CA (US);

Uma Durairajan, Sunnyvale, CA (US);

Weiguang Lu, San Jose, CA (US);

Karthy Rajasekharan, Cupertino, CA (US);

Kumar Rahul, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); H03K 19/177 (2006.01); G06F 3/06 (2006.01); G06F 13/40 (2006.01); G11C 7/10 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G01R 31/318516 (2013.01); G06F 3/0604 (2013.01); G06F 3/0635 (2013.01); G06F 3/0673 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G11C 7/106 (2013.01); G11C 7/1012 (2013.01); H03K 19/1776 (2013.01); H03K 19/17776 (2013.01);
Abstract

In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.


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