The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Jul. 20, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Norio Fujita, Shiga-Ken, JP;

Masahiro Hori, Shiga-ken, JP;

Masahiro Murakami, Kyoto, JP;

Junka Okazawa, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 3/06 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 1/324 (2013.01); G06F 3/0625 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 11/3027 (2013.01); G06F 13/161 (2013.01); G06F 13/364 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.


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