The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Mar. 29, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Fan Zhang, Fremont, CA (US);

Chenrong Xiong, San Jose, CA (US);

Yu Cai, San Jose, CA (US);

Aman Bhatia, San Jose, CA (US);

HyungSeok Kim, Santa Clara, CA (US);

June Lee, Sunnyvale, CA (US);

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1048 (2013.01); G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0644 (2013.01); G06F 3/0683 (2013.01); G06F 11/102 (2013.01);
Abstract

A memory device including a memory having a plurality of memory cells for storing data. The memory device includes a controller communicatively coupled to the memory and configured to organize the data as a plurality of stripes. Each individual stripe of the plurality of stripes includes a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells. Stripe lengths (number of data groups) for individual stripes are determined by the controller based on detecting a condition associated with one or more data groups of the plurality of data groups. At least one data group of the plurality of data groups for each of the individual stripes includes parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.


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