The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Aug. 28, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si OT, KR;

Inventors:

Sun-young Lim, Hwaseong-si, KR;

Young-jin Cho, Seoul, KR;

Jang-seok Choi, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/073 (2013.01); G06F 3/0619 (2013.01); G06F 11/1072 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01);
Abstract

A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.


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