The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Aug. 14, 2014
Applicants:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Seoul National University R&db Foundation, Seoul, KR;

Inventors:

Hansu Cho, Hwaseong-si, KR;

Brent ByungHoon Kang, Fairfax, VA (US);

Yunheung Paek, Seoul, KR;

Seungwook Lee, Seoul, KR;

Junbum Shin, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/00 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 21/79 (2013.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/0619 (2013.01); G06F 3/0637 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/30 (2013.01); G06F 13/16 (2013.01); G06F 21/79 (2013.01); H04L 63/145 (2013.01);
Abstract

Provided is a method of memory access for a memory controller in an integrity monitoring system sharing memory with a host system. The memory access method may include: receiving a memory access command from a local processor of the integrity monitoring system; accessing a system memory of the host system according to the memory access command; receiving data corresponding to the memory access command from the host system; and forwarding the received data to the local processor, wherein the system memory includes a secure area, access to which is allowed when the memory controller receives a memory access command from the local processor. In a feature of the present invention, there are provided a method and apparatus that can monitor integrity of data processed in the host system in a SoC environment.


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