The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Aug. 21, 2017
Applicant:

Barefoot Networks, Inc., Palo Alto, CA (US);

Inventors:

Gregory C. Watson, Palo Alto, CA (US);

Julianne Zhu, Los Gatos, CA (US);

Ravindra Sunkad, Pleasanton, CA (US);

Steven Licking, San Jose, CA (US);

Sachin Bahadur, Santa Clara, CA (US);

Assignee:

BAREFOOT NETWORKS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/24 (2006.01); H04L 12/861 (2013.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 13/28 (2006.01); H04L 12/741 (2013.01);
U.S. Cl.
CPC ...
H04L 41/0816 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/4282 (2013.01); H04L 41/12 (2013.01); H04L 49/90 (2013.01); G06F 2213/0026 (2013.01); H04L 45/745 (2013.01);
Abstract

A method of incremental updating of a network forwarding element that includes (i) a set of data plane circuits with a set of ingress buffers and a group of configurable packet processing stages and (ii) a set of control plane circuits comprising a set of direct memory access (DMA) buffers. Configuration data for reconfiguring the data plane packet processing stages is loaded into the DMA buffers while the packet processing stages are processing the packets. The ingress buffers are configured to (i) pause sending the packets to the processing stages and (ii) continue storing the incoming packets while sending the data plane packets to the processing stages is paused. The configuration data is loaded from the DMA buffers into the packet processing stages. The ingress buffers are configured to resume sending the data packet plane packets to the packet processing stages.


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