The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Nov. 14, 2017
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

David A. Roberts, Boxborough, MA (US);

Andrew G. Kegel, Bellevue, WA (US);

Elliot H. Mednick, Boxborough, MA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G06F 17/50 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17732 (2013.01); G06F 15/7892 (2013.01); G06F 17/5045 (2013.01); H03K 19/1776 (2013.01); H03K 19/17728 (2013.01); H03K 19/17756 (2013.01);
Abstract

A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.


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