The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Sep. 07, 2017
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Navin Harwalkar, Austin, TX (US);

John M. Khoury, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03G 3/20 (2006.01); H02M 1/00 (2006.01); H02M 3/156 (2006.01); G05F 1/10 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
H03G 3/20 (2013.01); G05F 1/10 (2013.01); H03M 1/66 (2013.01);
Abstract

Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a programmable digital input signal is determined in a calibration mode and then applied to reference circuitry in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.


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