The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Aug. 23, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Makar Snai, Burdwan, IN;

Tonmoy Biswas, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H04B 1/40 (2015.01); H04W 88/08 (2009.01); H04W 88/02 (2009.01);
U.S. Cl.
CPC ...
H03F 3/45636 (2013.01); H03F 3/45183 (2013.01); H04B 1/40 (2013.01); H03F 2203/45082 (2013.01); H03F 2203/45292 (2013.01); H04W 88/02 (2013.01); H04W 88/08 (2013.01);
Abstract

Certain aspects of the present disclosure provide methods and apparatus for amplifying signals with an amplification circuit and improving a common-mode rejection ratio (CMRR) thereof. The amplification circuit generally includes a differential amplifier comprising a first pair of transistors and a second pair of transistors coupled to the first pair of transistors, where the gates of the first pair of transistors are coupled to respective differential input nodes. The amplification circuit also includes an auxiliary amplifier comprising a third pair of transistors corresponding to the first pair of transistors and a fourth pair of transistors corresponding to the second pair of transistors, where drains of the third and fourth pairs of transistors are coupled together and to gates of the second pair of transistors and where gates of the fourth pair of transistors are coupled together.


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