The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jan. 07, 2015
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventor:

Yuji Ebiike, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/47 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 29/0634 (2013.01); H01L 29/0653 (2013.01); H01L 29/0878 (2013.01); H01L 29/0886 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/41725 (2013.01); H01L 29/41741 (2013.01); H01L 29/45 (2013.01); H01L 29/47 (2013.01); H01L 29/66068 (2013.01); H01L 29/7806 (2013.01); H01L 29/872 (2013.01);
Abstract

A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween.


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