The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Sep. 08, 2017
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Sohyung Lee, Goyang-si, KR;

Youngyoung Chang, Goyang-si, KR;

Kwonshik Park, Seoul, KR;

Mincheol Kim, Paju-si, KR;

Jeongsuk Yang, Asan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/32 (2006.01); G02F 1/13 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); G02F 1/136213 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); G02F 1/1368 (2013.01); G02F 2001/134372 (2013.01); H01L 27/322 (2013.01); H01L 27/3265 (2013.01);
Abstract

A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode.


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