The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Apr. 16, 2018
Applicants:
International Business Machines Corporation, Armonk, NY (US);
Horacio Mendez, Austin, TX (US);
Inventors:
Terence B. Hook, Jericho, VT (US);
Horacio Mendez, Austin, TX (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/265 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/36 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 21/326 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/2652 (2013.01); H01L 21/326 (2013.01); H01L 21/823493 (2013.01); H01L 21/823807 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01); H01L 27/0925 (2013.01); H01L 29/0649 (2013.01); H01L 29/36 (2013.01);
Abstract
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.