The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Sep. 28, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kosuke Yanagidaira, Fujisawa, JP;

Chikaaki Kodama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/11519 (2017.01); H01L 27/11526 (2017.01); H01L 27/11529 (2017.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/48 (2013.01); H01L 23/522 (2013.01); H01L 27/0207 (2013.01); H01L 27/11519 (2013.01); H01L 27/11526 (2013.01); H01L 27/11529 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.


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