The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jan. 05, 2010
Applicants:

Kyoko Izuha, Kanagawa, JP;

Hiroaki Ammo, Kanagawa, JP;

Yoshiyuki Enomoto, Kumamoto, JP;

Inventors:

Kyoko Izuha, Kanagawa, JP;

Hiroaki Ammo, Kanagawa, JP;

Yoshiyuki Enomoto, Kumamoto, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/5222 (2013.01); H01L 27/0207 (2013.01); H01L 28/40 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.


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