The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Aug. 11, 2014
Applicants:

Ellis Robinson Giles, Houston, TX (US);

Peter Joseph Varman, Houston, TX (US);

Inventors:

Ellis Robinson Giles, Houston, TX (US);

Peter Joseph Varman, Houston, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G11C 14/00 (2006.01); G11C 11/15 (2006.01); G06F 12/0815 (2016.01); G11C 13/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0045 (2013.01); G06F 12/0815 (2013.01); G11C 11/15 (2013.01); G06F 3/06 (2013.01); G11C 13/0002 (2013.01);
Abstract

Emerging byte-addressable persistent memory technologies, generically referred to as Storage Class Memory, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Unifying storage and memory into a memory tier that can be accessed directly requires additional burden to ensure that groups of memory operations to persistent or nonvolatile memory locations are performed sequentially, atomically, and not caught in the cache hierarchy. The present invention provides a lightweight solution for the atomicity and durability of write operations to nonvolatile memory, while simultaneously supporting fast paths through the cache hierarchy to memory. The invention includes a hardware-supported solution with modifications to the memory hierarchy comprising a victim cache and additional memory controller logic. The invention also includes a software only method and system that provides atomic persistence to nonvolatile memory using a software alias in DRAM and log in nonvolatile memory.


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