The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Apr. 27, 2015
Applicant:

Hewlett-packard Development Company, L.p., Houston, TX (US);

Inventors:

Ning Ge, Palo Alto, CA (US);

Zhiyong Li, Palo Alto, CA (US);

Jianhua Yang, Amherst, MA (US);

R. Stanley Williams, Portola Valley, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 45/00 (2006.01); G03F 7/16 (2006.01); G11C 13/00 (2006.01); G11C 19/28 (2006.01); B41J 2/045 (2006.01); B41J 2/14 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G03F 7/16 (2013.01); B41J 2/0458 (2013.01); B41J 2/04541 (2013.01); B41J 2/04543 (2013.01); B41J 2/14129 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 19/28 (2013.01); H01L 27/10817 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 28/87 (2013.01); H01L 28/91 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1675 (2013.01); H01L 45/1683 (2013.01); B41J 2202/13 (2013.01); G11C 13/0023 (2013.01); G11C 2213/15 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.


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