The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Oct. 31, 2017
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Sul Lee, Goyang-si, KR;

Sunhwa Lee, Paju-si, KR;

Seongjun Cho, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/133345 (2013.01); G02F 1/1368 (2013.01); G02F 1/13624 (2013.01); G02F 1/136286 (2013.01); H01L 27/1214 (2013.01); G02F 2001/134372 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); G02F 2201/40 (2013.01); G02F 2202/104 (2013.01);
Abstract

The present disclosure relates to an ultra high resolution liquid crystal display having a compensation thin film transistor. The present disclosure provides an ultra high density liquid crystal display comprising: a gate line on a substrate; a first gate insulating layer on the gate line; a first semiconductor layer crossing the gate line on the first gate insulating layer; a second gate insulating layer on the first semiconductor layer; a second semiconductor layer crossing the gate line on the second gate insulating layer; an intermediate insulating layer on the second semiconductor layer; a data line connected to the first semiconductor layer on the intermediate insulating layer; and a drain electrode connected to the second semiconductor layer on the intermediate insulating layer.


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