The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Jun. 22, 2015
Micronas Gmbh, Freiburg, DE;
Joachim Ritter, Loerrach, DE;
TDK-Micronas GmbH, Freiburg, DE;
Abstract
An arrangement for testing integrated circuits includes an integrated test circuit and a cluster which has at least one integrated circuit and a second integrated circuit. The first integrated circuit is provided in a first component region of a wafer, and the second integrated circuit in a second component region. The first component region and the second component region are spaced a distance apart by a scribe line of the wafer. The integrated test circuit is connected to the first integrated circuit via a first test line section, and the second integrated circuit is connected to the first test line section via a first connecting line that has a first well in the semiconductor material, the first well extending continuously in the wafer from the first component region over the scribe line to the second component region, the first well being electrically insulated from a substrate of the wafer.