The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jun. 18, 2014
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Unitec Semiconductores S.a., Rio de Janerio, BR;

Inventors:

Emmanuel Delamarche, Rueschlikon, CH;

Tobias Guenzler, Rio de Janerio, BR;

Yuksel Temiz, Rueschlikon, CH;

Tino Treiber, Rio de Janerio, BR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B01L 3/00 (2006.01); H01L 21/302 (2006.01); B81C 1/00 (2006.01); B05D 1/00 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
B01L 3/502707 (2013.01); B05D 1/005 (2013.01); B81C 1/00119 (2013.01); H01J 37/32009 (2013.01); B01L 2200/0668 (2013.01); B01L 2200/0684 (2013.01); B01L 2200/12 (2013.01); B01L 2300/0645 (2013.01); B01L 2300/0816 (2013.01); B01L 2300/0887 (2013.01); B01L 2300/161 (2013.01); B01L 2400/0406 (2013.01); B01L 2400/0418 (2013.01); B81B 2201/058 (2013.01); B81B 2203/04 (2013.01); H01J 2237/334 (2013.01);
Abstract

The present invention is notably directed to method of fabrication of a microfluidic chip (), comprising: providing (S-S) a substrate (), a face (F) of which is covered by an electrically insulating layer (); obtaining (S) a resist layer () covering one or more selected portions (P) of the electrically insulating layer (), at least a remaining portion (P) of said electrically insulating layer () not being covered by the resist layer; partially etching (S) with a wet etchant (E) a surface of the remaining portion (P) of the electrically insulating layer () to create a recess () and/or an undercut () under the resist layer (); depositing (S) the electrically conductive layer () on the etched surface (), such that the electrically conductive layer reaches the created recess () and/or undercut (); and removing (S) the resist layer () to expose a portion (P) of the electrically insulating layer adjoining a contiguous portion (P) of the electrically conductive layer (). The present invention is further directed to microfluidic chips obtainable by such methods.


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