The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Dec. 20, 2017
Applicant:

Avnera Corporation, Beaverton, OR (US);

Inventors:

Wai Lee, Portland, OR (US);

Jianping Wen, Tigard, OR (US);

Garry N. Link, Pacific City, OR (US);

Assignee:

AVNERA CORPORATION, Beaverton, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/46 (2006.01); H03M 1/08 (2006.01); H03M 1/44 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/462 (2013.01); H03M 1/0678 (2013.01); H03M 1/08 (2013.01); H03M 1/0863 (2013.01); H03M 1/442 (2013.01); H03M 1/468 (2013.01);
Abstract

The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.


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