The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

May. 28, 2017
Applicant:

Xiamen Sanan Optoelectronics Technology Co., Ltd., Xiamen, CN;

Inventors:

Zhibo Xu, Xiamen, CN;

Sheng-wei Chou, Xiamen, CN;

Chih-ching Cheng, Xiamen, CN;

Xiao Wang, Xiamen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/44 (2010.01); H01L 29/06 (2006.01); H01L 33/02 (2010.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 33/44 (2013.01); H01L 21/022 (2013.01); H01L 21/02172 (2013.01); H01L 29/0653 (2013.01); H01L 33/005 (2013.01); H01L 33/02 (2013.01);
Abstract

A semiconductor element has a metal protective layer and a metal oxide protective layer formed on the substrate to prevent the Si substrate surface from forming an amorphous layer; and a transition layer to reduce lattice difference between the metal oxide protective layer and the III-V-group buffer layer, thus improving crystal quality of the III-V-group buffer layer. A fabrication method can avoid formation of amorphous layers and cracks surrounding the Si substrate surface. A light-emitting diode (LED) element or a transistor element can be formed by depositing a high-quality multi-layer buffer structure via PVD and forming a GaN, InGaN or AlGaN epitaxial layer thereon.


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