The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Apr. 01, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Tae-Kyun Kim, Gyeonggi-do, KR;

Jin-Hee Cho, Gyeonggi-do, KR;

Jun-Gi Choi, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 11/36 (2006.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01); G11C 29/12 (2006.01); G11C 29/14 (2006.01); G11C 29/18 (2006.01); G11C 29/36 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G06F 11/1451 (2013.01); G06F 11/3668 (2013.01); G11C 29/04 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/18 (2013.01); G11C 29/36 (2013.01); G11C 29/44 (2013.01); G11C 29/46 (2013.01); G11C 29/50016 (2013.01); G11C 29/72 (2013.01); G11C 29/76 (2013.01); G11C 29/783 (2013.01); G06F 2201/805 (2013.01); G06F 2201/84 (2013.01); G11C 2029/0403 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/1806 (2013.01);
Abstract

A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.


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