The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Jul. 20, 2017
Applicant:

Ip Gem Group, Llc, Irvine, CA (US);

Inventors:

Alessia Marelli, Dalmine, IT;

Rino Micheloni, Turate, IT;

Assignee:

IP GEM GROUP, LLC, Irvine, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); G06F 11/07 (2006.01); G11C 16/34 (2006.01); G11C 29/52 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01); G11C 29/50 (2006.01); G11C 11/56 (2006.01); G11C 29/26 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 11/076 (2013.01); G11C 16/3427 (2013.01); G11C 16/3495 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/12005 (2013.01); G11C 29/4401 (2013.01); G11C 29/46 (2013.01); G11C 29/50004 (2013.01); G11C 29/50016 (2013.01); G11C 29/52 (2013.01); G11C 11/5642 (2013.01); G11C 16/349 (2013.01); G11C 29/26 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/4402 (2013.01); G11C 2029/5002 (2013.01);
Abstract

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.


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