The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Oct. 16, 2017
Applicant:

Sii Semiconductor Corporation, Chiba-shi, Chiba, JP;

Inventor:

Makoto Mitani, Chiba, JP;

Assignee:

ABLIC INC., Chiba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 16/14 (2006.01); H02M 3/07 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 5/145 (2013.01); G11C 16/14 (2013.01); H02M 3/07 (2013.01); H02M 3/073 (2013.01); G11C 16/30 (2013.01); H02M 2003/075 (2013.01); H02M 2003/078 (2013.01);
Abstract

To obtain a booster circuit capable of reducing voltage stress applied to a booster cell, provided is a booster circuit including a plurality of booster cells connected in series. Each of the plurality of booster cells includes a charge transfer transistor connected between an input terminal and an output terminal, and a boost capacitor connected between the input terminal and a clock terminal. Among the plurality of booster cells, a plurality of booster cells at least in a last stage are connected in parallel so that the plurality of booster cells connected in parallel are connected to a booster cell in a previous stage of the last stage by switching the plurality of booster cells in the last stage in accordance with a boosting operation.


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