The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Feb. 03, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Assaf Shacham, Zichron Yaakov, IL;

Eyal Skulsky, Zichron Yaakov, IL;

Shaul Yohai Yifrach, Haifa, IL;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 12/14 (2006.01); G06F 13/38 (2006.01); G06F 21/85 (2013.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 12/1408 (2013.01); G06F 12/1466 (2013.01); G06F 13/385 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 21/602 (2013.01); G06F 21/85 (2013.01); G06F 2212/402 (2013.01);
Abstract

Aspects disclosed in the detailed description include inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe). In this regard, in one aspect, an ICE is provided in a PCIe root complex (RC) in a host system. The PCIe RC is configured to receive at least one transport layer packet (TLP), which includes a TLP prefix, from a storage device. In a non-limiting example, the TLP prefix includes transaction-specific information that may be used by the ICE to provide data encryption and decryption. By providing the ICE in the PCIe RC and receiving the transaction-specific information in the TLP prefix, it is possible to encrypt and decrypt data in the PCIe RC in compliance with established standards, thus ensuring adequate protection during data exchange between the PCIe RC and the storage device.


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