The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Feb. 28, 2017
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventor:

Jaroslaw Topp, Renningen, DE;

Assignee:

ROBERT BOSCH GMBH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 8/52 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3017 (2013.01); G06F 8/52 (2013.01); G06F 9/3001 (2013.01); G06F 9/30021 (2013.01);
Abstract

A method is described for operating a microprocessor, in which a conversion software executed in the microprocessor carries out a binary translation, in the course of which a source instruction that is encoded according to a first instruction-set architecture is translated into a target instruction in a binary manner, which is encoded according to a second instruction-set architecture, and the target instruction translated by the translation software into the second instruction-set architecture being replicated, and in this replicated target instruction a memory area which is to be accessed in the course of the execution of the target instruction is replaced by a second memory area, and the target instruction and the copied target instruction is executed by the microprocessor. With the aid of the method, a temporal redundancy is achieved by a (temporally) parallel execution of the target instruction on a processor core and a local or regional redundancy by a parallel execution of the target instruction on different processor cores.


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