The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Apr. 23, 2014
Applicant:

Hitachi Automotive Systems, Ltd., Hitachinaka-shi, Ibaraki, JP;

Inventors:

Miki Hiraoka, Tokyo, JP;

Shiro Yamashita, Tokyo, JP;

Tomishige Yatsugi, Hitachinaka, JP;

Assignee:

Hitachi Automotive Systems, Ltd., Hitachinaka-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H05K 1/111 (2013.01); H05K 3/3442 (2013.01); H05K 2201/09381 (2013.01); H05K 2201/09427 (2013.01); H05K 2201/09663 (2013.01); H05K 2201/10621 (2013.01); H05K 2201/10636 (2013.01); Y02P 70/611 (2015.11); Y02P 70/613 (2015.11);
Abstract

The objective of the present invention is to improve reliability in a solder connection portion between an electronic component and a wiring pattern. A pair of wiring patterns (A andB) are formed on a circuit wiring board () with an insulation layer () therebetween. Each wiring pattern (A andB) has a land (or) and a wiring portion (or) that is narrower than the land. By way of solder (), a chip component () is soldered to the lands (and). The x (width) direction center (Xa) of each connection portion () where a respective wiring portion (or) is connected to a respective land (or) is disposed at a position that is outside of both the region in which a region of predetermined width (Wc) of the chip component () extends in the x (longitudinal) direction, and the region in which a region of predetermined length (Lc) of the chip component () extends in a y (transverse) direction.


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