The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Sep. 24, 2015
Applicant:

Nihon Dempa Kogyo Co., Ltd., Tokyo, JP;

Inventors:

Hiroyuki Demura, Saitama, JP;

Kaoru Kobayashi, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 21/00 (2006.01); H03L 7/18 (2006.01); H03L 7/091 (2006.01); G06F 1/02 (2006.01); H03L 7/183 (2006.01);
U.S. Cl.
CPC ...
H03L 7/18 (2013.01); G06F 1/022 (2013.01); H03L 7/091 (2013.01); H03L 7/183 (2013.01);
Abstract

The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer, a DDSoperates based on a clock signal to generate a reference frequency signal with a predetermined reference frequency, and clock signal supply unitsandswitch the clock signals that have different clock frequencies to supply to the DDS. When the clock signals are switched to operate the DDS, the storage unitstores a combination of a clock frequency f, a reference frequency f, and a dividing number N in association with an output frequency fof the frequency synthesizersuch that a spurious frequency does not exist within a predetermined frequency range and a dividing number of a variable frequency dividerdisposed on a PLL circuitis minimum. Setting unitsandread setting items stored in the storage unitto set respective units.


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