The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Apr. 07, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do OT, KR;

Inventors:

Chun-Ju Shen, San Jose, CA (US);

Jenn-Gang Chern, Redwood City, CA (US);

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 7/08 (2006.01); H03K 5/156 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 7/08 (2013.01); H03K 5/135 (2013.01); H03K 5/1565 (2013.01); H03K 2005/00052 (2013.01); H03K 2005/00058 (2013.01);
Abstract

The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.


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