The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Oct. 23, 2017
Applicant:
Rf Pixels, Inc., Fremont, CA (US);
Inventors:
Siva V. Thyagarajan, San Jose, CA (US);
Ali M. Niknejad, Berkeley, CA (US);
Sriramkumar Venugopalan, Campbell, CA (US);
Assignee:
RF Pixels, Inc., Fremont, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/04 (2006.01); H03F 1/02 (2006.01); H03F 3/21 (2006.01); H03F 3/24 (2006.01); H03F 3/217 (2006.01); H03G 3/30 (2006.01); H03F 3/19 (2006.01);
U.S. Cl.
CPC ...
H03F 1/02 (2013.01); H03F 1/0277 (2013.01); H03F 3/19 (2013.01); H03F 3/211 (2013.01); H03F 3/2175 (2013.01); H03F 3/24 (2013.01); H03F 3/245 (2013.01); H03G 3/3042 (2013.01); H04B 1/0458 (2013.01); H03F 2200/451 (2013.01); H04B 2001/045 (2013.01); H04B 2001/0416 (2013.01);
Abstract
An apparatus, comprising has an array of power amplifiers. A power detector collects a power signal applied to the array of power amplifiers. Digital logic is connected to the array of power amplifiers and the power detector. The digital logic is configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers. Each array pattern in the set of array patterns includes at least one operative power amplifier.