The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Oct. 14, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Takatoshi Orui, Sakai, JP;

Shigeyasu Mori, Sakai, JP;

Makoto Nakazawa, Sakai, JP;

Fumiki Nakano, Sakai, JP;

Kiyoshi Minoura, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 3/44 (2006.01); H01Q 3/34 (2006.01); H01L 23/66 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01Q 13/10 (2006.01); H01Q 21/00 (2006.01); H01Q 21/06 (2006.01); H01Q 21/20 (2006.01); H01Q 21/24 (2006.01);
U.S. Cl.
CPC ...
H01Q 3/44 (2013.01); H01L 23/66 (2013.01); H01L 27/124 (2013.01); H01L 27/1262 (2013.01); H01Q 3/34 (2013.01); H01Q 13/10 (2013.01); H01Q 21/0012 (2013.01); H01Q 21/064 (2013.01); H01L 27/1218 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78669 (2013.01); H01L 29/78678 (2013.01); H01L 2223/6677 (2013.01); H01Q 21/20 (2013.01); H01Q 21/24 (2013.01);
Abstract

A scanned antenna () is a scanned antenna including antenna elements (U) arranged together, the scanned antenna comprising: a TFT substrate including a first dielectric substrate (), TFTs, gate bus lines, source bus lines, and patch electrodes (); a slot substrate () including a second dielectric substrate (), and a slot electrode () formed on a first primary surface of the second dielectric substrate; a liquid crystal layer (LC) provided between the TFT substrate and the slot substrate; and a reflective conductive plate () arranged so as to oppose a second primary surface of the second dielectric substrate () with a dielectric layer () interposed therebetween, the second primary surface being on an opposite side from the first primary surface. The TFT substrate (TFT substrate portion (Cb)) includes a terminal region (TR) outside of the seal portion (), and the gate bus lines or the source bus lines are connected to gate terminal portions or source terminal portions formed in the terminal region via a transparent conductive layer () provided between the seal portion () and the TFT substrate.


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